During ESD, large currents can flow through an IC and can potentially cause damage. Damage can occur within the device that conducts the current, as well as in devices that see a significant voltage drop due to the large current flow. To avoid damage due to an ESD event, clamps may be added to the IC. These clamps shunt the large ESD current without causing high voltage over sensitive nodes of the IC.
One ESD clamp design consideration may be to prevent the clamp from accidentally shunting current during normal operating conditions. Accidentally shunting current during normal operating conditions may result in a temporary loss of function and may require human or other IC interaction to restore the normal operation. Furthermore, a clamp triggering during normal operation may cause permanent damage to the IC due to excess current draw. If the clamp triggers in low conductive (shunt) mode during normal operation, the energy of the current through the clamp may be too high such that temporary or permanent damage can occur. An increased (supply) current during normal operation caused by faulty triggering of the ESD device may be called a latch-up event, and might result in temporary loss of function, temporary damage, or permanent damage to the IC. EOS may be caused by unwanted high voltages at IC pins.
A known way to overcome these issues may include creating ESD clamps with a high clamping voltage. The clamping voltage of the clamp may be the lowest voltage at which the device can sustain its high conductive state. By increasing the clamping voltage above the supply level, the ESD clamp may be designed to release from the latched state even if triggered during normal operation, such that the loss of function may be temporary.
For some applications, such as automotive, it may be preferable to have a clamping voltage much higher than the supply level to avoid temporary loss of function due to noise spikes, or to allow off-chip ESD protection to shunt system-level ESD currents without triggering the on-chip ESD protection.
A further design constraint for the ESD protection clamp may include low standby or leakage current. For some applications, the amount of capacitance added to the pad may be minimized as well.
One way to provide ESD protection may be to use Zener diodes or reverse diodes as ESD clamps. But the performance of these clamps may be very low and a large area may be needed. Very often additional layers may be needed to tune the clamping voltage.
The performance per area could be improved by using a gate-grounded n-type metal oxide semiconductor (GGNMOS), but oxide reliability issues may occur and in high voltage applications the NMOS may not survive snapback.
There is a need for improved ESD protection with a high clamping voltage and efficient area usage without oxide reliability issues.